The present invention relates to an image processing circuit in the monitor of a personal computer, an intelligent terminal, a TV telephone or a smart TV and, more particularly, to a process for processing an image to an arbitrary size and superposing it.
In the prior art, there is an image processing system which is enabled to operate a personal computer while observing a TV program by superimposing the picture of the TV with a predetermined size and in a predetermined position on the monitor frame of the personal computer.
FIG. 21 is a block diagram showing the image processing system of the prior art. In FIG. 21: reference numeral 100 designates a video decoder for separating a first video signal VS1 into a first synchronizing signal SS1 and a first luminance signal LS1; numeral 200 designates an analog-digital converter (which will be shortly referred to as an xe2x80x9cADCxe2x80x9d) for digitizing the first luminance signal LS1; numeral 300 designates a video memory for storing the digitized first luminance signal LS1; numeral 340 designates a write control unit for controlling the writing of the first luminance signal LS1 in the video memory 300; numeral 350 designates a read control unit for controlling the reading of the first luminance signal LS1 out of the video memory 300; numeral 400 designates a digital-analog converter (which will be shortly referred to as a xe2x80x9cDACxe2x80x9d) for converting to analog the first luminance signal LS1 read out from the video memory 300; numeral 600 designates a CPU control unit; numeral 630 designates a multiplexer; numeral 640 designates a video decoder unit for separating a third video signal VS3 into a third synchronizing signal SS3 and a third luminance signal LS3; and numeral 500 designates a mixing control unit for mixing the first luminance signal LS1 and the third luminance signal LS3 to output a fourth luminance signal LS4.
In this video processing circuit of the prior art, the video decoder 100 separates the video signal VS1 into the synchronizing signal SS1 and the luminance signal LS1, and the ADC 200 digitizes and writes the luminance signal LS1 in the video memory 300.
At this time, the write control unit 340 outputs a timing clock for controlling the operations of the ADC 200 and the video memory 300 on the basis of the synchronizing signal SS1.
Here, the second luminance signal LS2 outputted from the CPU control unit 600 can be written in the video memory 300.
Moreover, the read control unit 350 reads out the first luminance signal LS1 (or the second luminance signal LS2) written in the video memory 300 through the multiplexer 630. The DAC 400 converts to analog the first luminance signal LS1 read out from the video memory 300. The mixing control unit 500 mixes the first luminance signal LS1 and the third luminance signal LS3 to output the fourth luminance signal LS4 in which an image corresponding to the first luminance signal LS1 is superimposed on the image corresponding to the third luminance signal LS3.
For a still image, on the other hand, a CPU 620 monitors the operations of the video decoder unit 100. If this video decoder unit 100 outputs a vertical synchronizing signal, the CPU 620 interrupts the digitize control by the ADC 200 during the vertical blanking period in the video signal.
In this still image, too, there can be obtained the fourth luminance signal LS4 in which the image corresponding to the first luminance signal LS1 is superimposed upon the image corresponding to the third luminance signal LS3.
When, moreover, letters or special shapes are to be superimposed upon the image corresponding to the first luminance signal LS1, the CPU control unit 600 writes the shape data of the letters or special shapes in the video memory 300.
Here, the image processing system of the prior art, as shown in FIG. 21, is troubled by a problem that it cannot cope in the least with the multipurpose specifications such as the display by an arbitrary resolution corresponding to a smart image to be developed in the near future, the conversion of an arbitrary aspect ratio, the control of display in an arbitrary position, or the superimpose.
For the multi-purpose specifications, moreover, the price for the system rises as high as several hundreds to thousands yens as in the TV broadcasting system used at present in the commercial broadcasting stations.
This raises a problem that fundamental technical innovations are required for the level of the home appliances.
Generally speaking, on the other hand, the video memory 300 has to be refreshed because it is constructed of a dynamic memory.
For this necessity, a clock signal for refreshing the video memory 300 is fed to the serial ports of the video memory 300. This clock signal has a frequency of 10 (MHz) or more, for example.
In case, therefore, the serial output at the side of the multiplexer 630 has a clock of several hundreds (KHz) to several (MHz), a frequency of 10 (MHz) or more has to be supplied from the aforementioned serial output other than that at the side of the DAC 400.
This serial output other than that at the side of the DAC 400 has to be merely the refreshing clock aiming at no output.
If the video data of the video memory 300 is to be read out by the CPU control unit 600, the multiplexer 630 has to be switched to read out the video data from the CPU control 600 so that the video data are not sent to the DAC 400. This raises another problem that the image coming from the DAC 400 becomes the fourth luminance signal LS4 in the blanked state even if it is superimposed upon the third luminance signal LS3.
Still another problem is that it is impossible for the CPU to read the CPU control 600 by the operations always having a frequency of 10 (MHz) or more than that of the aforementioned serial output other than that at the side of the DAC 400.
For the still image, moreover, the CPU control unit 600 has to monitor the a vertical synchronizing signal VS1 thereby to raise a further problem that the CPU control unit 600 has to require a standby time of several tens mS in the worst case.
Even if, moreover, the CPU control unit 600 is equipped with a high-speed IC such as a digital signal processor (which is called the xe2x80x9cDSPxe2x80x9d), it takes several tens (xcexcs) to rewrite the letters or special shapes.
In case, on the other hand, the third luminance signal LS3 is related to one corresponding to a motion picture, there is required a time period for reducing the frame number of the third luminance signal LS3 and to rewrite the stored content of the video memory 300 by the CPU 620.
It is impossible to scroll the letters or special shapes vertically and horizontally in the third luminance signal LS3.
The present invention has been conceived to solve the above-specified problems and has an object to provide an image processing system for achieving the following objects:
(1) to realize an arbitrary resolution of the image, an arbitrary area designation; a location of an arbitrary memory or a conversion to an arbitrary aspect ratio easily at the level of home appliances;
(2) to read out the luminance signals of the video memory easily from a control system of irregular time such as the CPU without any interruption of the monitor output function of the video memory;
(3) to eliminate any necessary for the standby for the still image by the CPU control unit 600;
(4) to rewrite the displayed content in real time of the superimposed display frame; and
(5) to realize the above-specified functions at the price at the level of the home appliances.
According a first mode of the present invention, there is provided an image processing system comprising: decode means for separating a first video signal into a first luminance signal, a first horizontal synchronizing signal and a first vertical synchronizing signal; analog-digital conversion means for digitizing said first luminance signal; memory means for storing the digitized first luminance signal; digital-analog conversion means for reading and analogly converting the luminance signal stored by said memory means; mixing means for either the luminance signal read out and analogly converted by said memory means or a second luminance signal selectively as a third luminance signal; and control means for outputting control signals to control said decode means, said analog-digital conversion means, said memory means, said digital-analog conversion means and said mixing means.
In a second mode of the present invention, said analog-digital conversion means, said memory means, said digital-analog conversion means, said mixing means and said control means are constructed on a extended slot card.
In a third mode of the present invention, said control means includes: operation means for inputting the position, size and timing for displaying an image corresponding to said first luminance signal to an image corresponding to said third luminance signal; and a device driver disposed in an operating system for outputting the signals corresponding to the position, size and timing, which are to be inputted by said operating means, to said decode means, said memory means, said digital-analog conversion means and mixing means.
According to a fourth mode of the present invention, said memory means includes a video memory for storing the first luminance signal, which is digitized by said analog-digital conversion means, in an area of the address, which is specified by a write shift signal and a write line increment signal, when a write enable signal is outputted, such that a horizontal address is reset by a horizontal write clear signal whereas a vertical address is reset by a vertical write clear signal, when said first luminance signal is to be written, so that said horizontal address is set at the unit of a block of a predetermined dot number by an address signal and incremented by said write shift signal and so that said vertical address is incremented by said write increment signal, and said analog-digital conversion means includes: an analog-digital conversion circuit for analog-digital converting said first luminance signal; a horizontal write dot clock generator synchronized with said first horizontal synchronizing signal for outputting a horizontal write dot clock signal having a frequency predetermined times as high as that of said first horizontal synchronizing signal and based upon said block unit as the analog-digital conversion clock signal of said analog-digital conversion means and a basic synchronizing signal having a predetermined frequency as said write shift signal; a horizontal write starting counter reset by said first horizontal synchronizing signal for counting the clock number of said horizontal write dot clock signal to output a horizontal write starting signal for starting the writing of said first luminance signal in said image memory and said horizontal write clear signal when said counted value reaches a preset value; a horizontal write number counter reset by said first horizontal synchronizing signal for counting the clock number of said horizontal write dot clock signal, after the output of said horizontal write starting signal, to output a horizontal write number signal for inhibiting the write of said first luminance signal in said video memory when said counted value reaches a predetermined value; a vertical write offset counter reset by said first vertical synchronizing signal for outputting a vertical write offset signal of the clock number of the preset value, which is synchronized with said basic synchronous signal, as said write line increment signal; a vertical write line clock generator synchronized with said first vertical synchronizing signal for outputting a vertical write line clock signal having a frequency of predetermined times as high as that of said vertical synchronizing signal as said write line increment signal; a vertical write starting counter reset by said first vertical synchronizing signal for counting the clock number of said first horizontal synchronizing signal to output a vertical write starting signal for starting the writing of said luminance signal in said video memory when said counted value reaches a preset value; a vertical write number counter reset by said vertical synchronizing signal for starting the counting of the clock number of said vertical write line clock signal, after the output of said vertical write starting signal, to output a vertical write number signal for inhibiting the writing of said first luminance signal in said video memory when said counted values reaches a preset value; and write control means for outputting said write enable signal on the basis of said first vertical synchronizing signal, said horizontal write clear signal, said horizontal write dot clock signal, said horizontal write starting signal, said horizontal write number signal, said vertical write starting signal, said vertical write number signal and said vertical write line clock signal to write the first luminance signal, which is digitized by said horizontal write dot clock signal, in the area of said video memory, which is specified by said address signal, said write shift signal and said write line increment signal, while said horizontal write starting signal and said vertical write starting signal are being outputted.
In a fifth mode of the present invention, said control means sets the value of said block, the frequency of said vertical write link clock signal, the preset value of said horizontal write starting counter, the preset value of said horizontal write number counter, the preset value of said vertical write starting counter and the preset value of said vertical write number counter.
In a sixth mode of the present invention, said control means includes image still means for outputting said first vertical synchronizing signal none of said video memory, said vertical write offset counter, said vertical write line clock generator, said vertical write starting counter and said vertical write number counter in accordance with the operations of said operation means.
In a seventh mode of the present invention, said memory means includes: a write control unit for controlling said video memory when said control means writes said second luminance signal in said video memory; luminance signal selecting means for outputting said first luminance signal and said second luminance signal selectively to said video memory; and a video memory control signal selecting unit for outputting a write control signal of said first luminance signal and a write control signal of said second luminance signal in a manner to correspond to the selected output of said first luminance signal and said second luminance signal.
In an eighth mode of the present invention, said memory means includes: an FIFO memory of first-in first-out type having at least a storage capacity equal to or more than that of said video memory for writing and reading said luminance signals asynchronously in and out of said video memory; a read control unit for controlling the reading of said luminance signal in said FIFO memory out of said video memory in accordance with the control of said control means; and an FIFO read control unit for controlling said FIFO memory.
In a ninth mode of the present invention, said video memory reads out said luminance signal from the address, which is specified by a read shift and a read line increment signal of said video memory, when a read enable signal is outputted, such that the horizontal address reset by said horizontal read clear signal whereas the vertical address is reset by the vertical read clear signal or said third vertical synchronizing signal, when said luminance signal stored in said video memory is to be read out, so that said horizontal address is incremented by said read shift signal whereas said vertical address is incremented by said read line increment signal, said digital-analog conversion means includes: a digital-analog conversion circuit for analogly converting and outputting the luminance signal which is read out from said video memory; a horizontal reference read dot clock generator for outputting a horizontal reference read dot clock signal synchronized with said third horizontal synchronizing signal; a first horizontal read starting counter reset by said third horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to output a first horizontal read starting signal for starting the reading of said luminance signal from said video memory and a horizontal read reset signal as said horizontal read clear signal when said counted value reaches a preset value; a second horizontal read starting counter reset by said third horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal, after the output of said first horizontal read starting signal, to output the second horizontal read starting signal when said counted value reaches a predetermined value; a horizontal read number counter reset by said third horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to inhibit the reading of the luminance signal, which is stored in said video memory, when said counted value reaches a preset value; a horizontal read dot clock generator for outputting a horizontal read dot clock signal synchronized with said third horizontal synchronizing signal; a vertical read offset counter reset by said third vertical synchronizing signal for outputting the vertical read offset signal as said vertical line increment signal on the basis of said horizontal reference read dot clock signal; a vertical blanking number counter reset by said third vertical synchronizing signal for counting the clock number of said third horizontal synchronizing signal to output a vertical blanking ending signal when said counted value indicates that a vertical back porch region has been passed; a vertical read starting counter reset by said third vertical synchronizing signal for counting the clock number of said third horizontal synchronizing signal, after the output of said vertical blanking ending signal, to output a vertical read starting signal for starting the reading the luminance signal from said video signal when said counted value reaches a preset value; a vertical read number counter reset by said third vertical synchronizing signal for counting the clock number of said third horizontal synchronizing signal, after the output of said vertical read starting signal, to output a vertical read number signal for inhibiting the reading of the luminance signal from said video memory, when said counted value reaches a preset value; a vertical read line clock generator for outputting the vertical read line clock signal, which is synchronized with said third vertical synchronizing signal, as said vertical line increment signal; a superimpose start signal output circuit for outputting a superimpose starting signal on the basis of said second horizontal read starting signal, said horizontal read number signal, said vertical read starting signal and said vertical read number signal; and a read enable signal output circuit for outputting said read enable signal on the basis of said third vertical synchronizing signal, said horizontal read reset signal, said vertical read line clock signal and said superimpose starting signal to read out the luminance signal from the area of said video memory, which is specified by either said horizontal reference read dot clock signal or said horizontal read dot clock signal and said read line increment signal, and said mixing means includes a video switch switched on the basis of said superimpose starting signal for selectively outputting the luminance signal, which is read out from said video memory and analogly converted by said digital-analog conversion circuit, and said third luminance signal.
In a tenth mode of the present invention, said horizontal reference read dot clock generator constructing the ninth mode of the present invention includes a PLL circuit for outputting a signal having a frequency several tens to thousands as high as that of said third horizontal synchronizing signal, said horizontal read dot clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third horizontal synchronizing signal, and said vertical read line clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third vertical synchronizing signal.
In an eleventh mode of the present invention, said control means constructing the tenth mode of the present invention sets the individual clock numbers which are counted by said first horizontal read starting counter, said horizontal read number counter, said vertical blanking number counter, said vertical read starting counter and said vertical read number counter.
In a twelfth mode of the present invention, said video memory reads out said luminance signal from the address, which is specified by a read shift signal and a read line increment signal of said video memory, when a read enable signal is outputted, such that the horizontal address reset by said horizontal read clear signal whereas the vertical address is reset by the vertical read clear signal or said third vertical synchronizing signal, when said luminance signal stored in said video memory is to be read out, so that said horizontal address is incremented by said read shift signal whereas said vertical address is incremented by said read line increment signal, said digital-analog conversion means includes: a digital-analog conversion circuit for analogly converting and outputting the luminance signal which is read out from said video memory; a horizontal reference read dot clock generator for outputting a horizontal reference read dot clock signal synchronized with said third horizontal synchronizing signal; a first horizontal read starting counter reset by said third horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to output a first horizontal read starting signal for starting the reading of said luminance signal from said video memory and a horizontal read reset signal as said horizontal read clear signal when said counted value reaches a preset value; a second horizontal read starting counter reset by said third horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal, after the output of said first horizontal read starting signal, to output the second horizontal read starting signal when said counted value reaches a predetermined value; a horizontal read number counter reset by said third horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to inhibit the reading of the luminance signal, which is stored in said video memory, when said counted value reaches a preset value; a horizontal read dot clock generator for outputting a horizontal read dot clock signal synchronized with said third horizontal synchronizing signal; a vertical read offset counter reset by said third vertical synchronizing signal for outputting the vertical read offset signal as said vertical line increment signal on the basis of said horizontal reference read dot clock signal; a vertical blanking number counter reset by said third vertical synchronizing signal for counting the clock number of said third horizontal synchronizing signal to output a vertical blanking ending signal when said countered value indicates that a vertical back porch region has been passed; a vertical read starting counter reset by said third vertical synchronizing signal for counting the clock number of said third horizontal synchronizing signal, after the output of said vertical blanking ending signal, to output a vertical read starting signal for starting the reading the luminance signal from said video signal when said counted value reaches a preset value; a vertical read number counter reset by said third vertical synchronizing signal for counting the clock number of said third horizontal synchronizing signal, after the output of said vertical read starting signal, to output a vertical read number signal for inhibiting the reading of the luminance signal from said video memory, when said counted value reaches a preset value; a vertical read line clock generator for outputting the vertical read line clock signal, which is synchronized with said third vertical synchronizing signal, as said vertical line increment signal; a superimpose start signal output circuit for outputting a superimpose starting signal on the basis of said second horizontal read starting signal, said horizontal read number signal, said vertical read starting signal and said vertical read number signal; and a read enable signal output circuit for outputting said read enable signal on the basis of said third vertical synchronizing signal, said horizontal read reset signal, said vertical read line clock signal and said superimpose starting signal to read out the luminance signal from the area of said video memory, which is specified by either said horizontal reference read dot clock signal or said horizontal read dot clock signal and said read line increment signal, and said mixing means includes: comparator means for comparing said third luminance signal and a predetermined reference signal; compared output starting signal output means for outputting a compared output starting signal for starting the output of the compared output of said comparator means; superimpose control means for outputting a first superimpose starting signal for starting the superimpose of the first luminance signal, which is read out from said video memory and analogly converted by said digital-analog converter, upon said third luminance signal and a second superimpose starting signal for starting the superimpose of said third luminance signal upon said first luminance signal; and superimpose control means for superimposing said third luminance signal upon the first luminance signal, which is superimposed upon said third luminance signal, on the basis of the compared output of said comparator means, said first superimpose starting signal and said second superimpose starting signal.
In a thirteenth mode of the present invention, said horizontal reference read dot clock generator constructing the twelfth mode of the present invention includes a PLL circuit for outputting a signal having a frequency several tens to thousands as high as that of said third horizontal synchronizing signal, said horizontal read dot clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third horizontal synchronizing signal, and said vertical read line clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third vertical synchronizing signal.
In a fourteenth mode of the present invention, said control means constructing the thirteenth mode of the present invention sets the individual clock numbers which are counted by said first horizontal read starting counter, said horizontal read number counter, said vertical blanking number counter, said vertical read starting counter and said vertical read number counter.
According to a fifteenth mode of the present invention, there is provided a digitize control system comprising: an analog-digital conversion circuit for analog-digital converting said first luminance signal; a video memory for storing the first luminance signal, which is digitized by said analog-digital conversion means, in an area of the address, which is specified by a write shift signal and a write line increment signal, when a write enable signal is outputted, such that a horizontal address is reset by a horizontal write clear signal whereas a vertical address is reset by a vertical write clear signal, when said first luminance signal is to be written, so that said horizontal address is set at the unit of a block of a predetermined dot number by an address signal and incremented by said write shift signal and so that said vertical address is incremented by said write increment signal; a horizontal write dot clock generator synchronized with said first horizontal synchronizing signal for outputting a horizontal write dot clock signal having a frequency predetermined times as high as that of said first horizontal synchronizing signal and based upon said block unit as the analog-digital conversion clock signal of said analog-digital conversion means and a basic synchronizing signal having a predetermined frequency as said write shift signal; a horizontal write starting counter reset by said first horizontal synchronizing signal for counting the clock number of said horizontal write dot clock signal to output a horizontal write starting signal for starting the writing of said first luminance signal in said image memory and said horizontal write clear signal when said counted value reaches a preset value; a horizontal write number counter reset by said first horizontal synchronizing signal for counting the clock number of said horizontal write dot clock signal, after the output of said horizontal write starting signal, to output a horizontal write number signal for inhibiting the write of said first luminance signal in said video memory when said counted value reaches a predetermined value; a vertical write offset counter reset by said first vertical synchronizing signal for outputting a vertical write offset signal of the clock number of the preset value, which is synchronized with said basic synchronous signal, as said write line increment signal; a vertical write line clock generator synchronized with said first vertical synchronizing signal for outputting a vertical write line clock signal having a frequency of predetermined times as high as that of said vertical synchronizing signal as said write line increment signal; a vertical write starting counter reset by said first vertical synchronizing signal for counting the clock number of said first horizontal synchronizing signal to output a vertical write starting signal for starting the writing of said luminance signal in said video memory when said counted value reaches a preset value; a vertical write number counter reset by said vertical synchronizing signal for starting the counting of the clock number of said vertical write line clock signal, after the output of said vertical write starting signal, to output a vertical write number signal for inhibiting the writing of said first luminance signal in said video memory when said counted value reaches a preset value; and write control means for outputting said write enable signal on the basis of said first vertical synchronizing signal, said horizontal write clear signal, said horizontal write dot clock signal, said horizontal write starting signal, said horizontal write number signal, said vertical write starting signal, said vertical write number signal and said vertical write line clock signal to write the first luminance signal, which is digitized by said horizontal write dot clock signal, in the area of said video memory, which is specified by said address signal, said write shift signal and said write line increment signal, while said horizontal write starting signal and said vertical write starting signal are being outputted.
In a sixteen mode of the present invention, said digitize control system includes digitize control means sets the value of said block, the frequency of said vertical write line clock signals the preset value of said horizontal write starting counter, the preset value of said horizontal write number counter, the preset value of said vertical write starting counter and the preset value of said vertical write number counter.
In a seventh mode of the present invention, said write control means includes image still means for outputting said first vertical synchronizing signal none of said video memory, said vertical write offset counter, said vertical write line clock generator, said vertical write starting counter and said vertical write number counter in accordance with the operations of said operation means.
In an eighteenth mode of the present invention, there is provided a superimpose control system comprising: a video memory storing a luminance signal for reading out said luminance signal from the address, which is specified by a read shift signal and a read line increment signal of said video memory, when a read enable signal is outputted, such that the horizontal address reset by said horizontal read clear signal whereas the vertical address is reset by the vertical read clear signal or a vertical synchronizing signal, so that said horizontal address is incremented by said read shift signal whereas said vertical address is incremented by said read line increment signal; a digital-analog conversion circuit for analogly converting and outputting the luminance signal which is read out from said video memory; a horizontal reference read dot clock generator for outputting a horizontal reference read dot clock signal synchronized with said horizontal synchronizing signal; a first horizontal read starting counter reset by said horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to output a first horizontal read starting signal for starting the reading of said luminance signal from said video memory and a horizontal read reset signal as said horizontal read clear signal when said counted value reaches a preset value; a second horizontal read starting counter reset by said horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal, after the output of said first horizontal read starting signal, to output the second horizontal read starting signal when said counted value reaches a predetermined value; a horizontal read number counter reset by said horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to inhibit the reading of the luminance signal, which is stored in said video memory, when said counted value reaches a preset value; a horizontal read dot clock generator for outputting a horizontal read dot clock signal synchronized with said horizontal synchronizing signal; a vertical read offset counter reset by said vertical synchronizing signal for outputting the vertical read offset signal as said vertical line increment signal on the basis of said horizontal reference read dot clock signal; a vertical blanking number counter reset by said vertical synchronizing signal for counting the clock number of said horizontal synchronizing signal to output a vertical blanking ending signal when said counted value indicates that a vertical back porch region has been passed; a vertical read starting counter reset by said vertical synchronizing signal for counting the clock number of said horizontal synchronizing signal, after the output of said vertical blanking ending signal, to output a vertical read starting signal for starting the reading the luminance signal from said video signal when said counted value reaches a preset value; a vertical read number counter reset by said vertical synchronizing signal for counting the clock number of said horizontal synchronizing signal, after the output of said vertical read starting signal, to output a vertical read number signal for inhibiting the reading of the luminance signal from said video memory, when said counted value reaches a preset value; a vertical read line clock generator for outputting the vertical read line clock signal, which is synchronized with said vertical synchronizing signal, as said vertical line increment signal; a superimpose start signal output circuit for outputting a superimpose starting signal on the basis of said second horizontal read starting signal, said horizontal read number signal, said vertical read starting signal and said vertical read number signal; a read enable signal output circuit for outputting said read enable signal on the basis of said vertical synchronizing signal, said horizontal read reset signal, said vertical read line clock signal and said superimpose starting signal to read out the luminance signal from the area of said video memory, which is specified by either said horizontal reference read dot clock signal or said horizontal read dot clock signal and said read line increment signal; and a video switch switched on the basis of said superimpose starting signal for selectively outputting the luminance signal, which is read out from said video memory and analogly converted by said digital-analog conversion circuit, and said luminance signal.
In a nineteenth mode of the present invention, said horizontal reference read dot clock generator constructing the eighteenth mode of the present invention includes a PLL circuit for outputting a signal having a frequency several hundreds as high as that of said third horizontal synchronizing signal, said horizontal read dot clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third horizontal synchronizing signal, and said vertical read line clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third vertical synchronizing signal.
In a twelfth mode of the present invention, said superimpose control system further comprises control means for setting the individual clock numbers which are counted by said first horizontal read starting counter, said horizontal read number counter, said vertical blanking number counter, said vertical read starting counter and said vertical read number counter.
In a twenty first mode of the present invention, there is provided a superimpose control system comprising: a video memory storing a luminance signal for reading out said luminance signal from the address, which is specified by a read shift signal and a read line increment signal of said video memory, when a read enable signal is outputted, such that the horizontal address reset by said horizontal read clear signal whereas the vertical address is reset by the vertical read clear signal or a vertical synchronizing signal, so that said horizontal address is incremented by said read shift signal whereas said vertical address is incremented by said read line increment signal; a digital-analog conversion circuit for analogly converting and outputting the luminance signal which is read out from said video memory; a horizontal reference read dot clock generator for outputting a horizontal reference read dot clock signal synchronized with said horizontal synchronizing signal; a first horizontal read starting counter reset by said horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to output a first horizontal read starting signal for starting the reading of said luminance signal from said video memory and a horizontal read reset signal as said horizontal read clear signal when said counted value reaches a preset value; a second horizontal read starting counter reset by said horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal, after the output of said first horizontal read starting signal, to output the second horizontal read starting signal when said counted value reaches a predetermined value; a horizontal read number counter reset by said horizontal synchronizing signal for counting the clock number of said horizontal reference read dot clock signal to inhibit the reading of the luminance signal, which is stored in said video memory, when said counted value reaches a preset value; a horizontal read dot clock generator for outputting a horizontal read dot clock signal synchronized with said horizontal synchronizing signal; a vertical read offset counter reset by said vertical synchronizing signal for outputting the vertical read offset signal as said vertical line increment signal on the basis of said horizontal reference read dot clock signal; a vertical blanking number counter reset by said vertical synchronizing signal for counting the clock number of said horizontal synchronizing signal to output a vertical blanking ending signal when said counted value indicates that a vertical back porch region has been passed; a vertical read starting counter reset by said vertical synchronizing signal for counting the clock number of said horizontal synchronizing signal, after the output of said vertical blanking ending signal, to output a vertical read starting signal for starting the reading the luminance signal from said video signal when said counted value reaches a preset value; a vertical read number counter reset by said vertical synchronizing signal for counting the clock number of said horizontal vertical signal, after the output of said vertical read starting signal, to output a vertical read number signal for inhibiting the reading of the luminance signal from said video memory, when said counted value reaches a preset value; a vertical read line clock generator for outputting the vertical read line clock signal, which is synchronized with said vertical synchronizing signal, as said vertical line increment signal; a superimpose start signal output circuit for outputting a superimpose starting signal on the basis of said second horizontal read starting signal, said horizontal read number signal, said vertical read starting signal and said vertical read number signal; a read enable signal output circuit for outputting said read enable signal on the basis of said vertical synchronizing signal, said horizontal read reset signal, said vertical read line clock signal and said superimpose starting signal to read out the luminance signal from the area of said video memory, which is specified by either said horizontal reference read dot clock signal or said horizontal read dot clock signal and said read line increment signal; comparator means for comparing said third luminance signal and a predetermined reference signal;
compared output starting signal output means for outputting a compared output starting signal for starting the output of the compared output of said comparator means; superimpose control means for outputting a first superimpose starting signal for starting the superimpose of the first luminance signal, which is read out from said video memory and analogly converted by said digital-analog converter, upon said third luminance signal and a second superimpose starting signal for starting the superimpose of said third luminance signal upon said first luminance signal; and superimpose control means for superimposing said third luminance signal upon the first luminance signal, which is superimposed upon said third luminance signal, on the basis of the compared output of said comparator means, said first superimpose starting signal and said second superimpose starting signal.
In a twenty second mode of the present invention, said horizontal reference read dot clock generator of the twenty first mode of the present invention includes a PLL circuit for outputting a signal having a frequency several hundreds as high as that of said third horizontal synchronizing signal, said horizontal read dot clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third horizontal synchronizing signal, and said vertical read line clock generator includes a PLL circuit for outputting a signal having a frequency a predetermined number of times as high as that of said third vertical synchronizing signal.
In a twenty third mode of the present invention, said superimpose control system further comprises control means for setting the individual clock numbers which are counted by said first horizontal read starting counter, said horizontal read number counter, said vertical blanking number counter, said vertical read starting counter and said vertical read number counter.
According to the first mode of the present invention thus constructed, the decoding means separates the first video signal into the first luminance signal, the first horizontal synchronizing signal and the first vertical synchronizing signal and analog-digital converts them, and the memory means stores the digitized first luminance signal.
Moreover, the digital-analog conversion means converts the digitized luminance signal stored in the memory means to analog, and the mixing means reads it out from the memory means so that either the analogly converted luminance signal or the second luminance signal is selectively outputted as the third luminance signal.
The aforementioned operations are controlled by the control means.
According to the second mode of the present invention thus constructed, moreover, the decoding means, the analog-digital conversion means, the memory means, the digital-analog conversion means, the mixing means and the control means constructing the first mode of the present invention are constructed over the one extended slot card.
According to the third mode of the present invention thus constructed, furthermore, the operation means inputs the position, size and timing of displaying the image corresponding to the first luminance signal with respect to the image corresponding to the third luminance signal. Then, the signal corresponding to the position, size and timing inputted to the device drive in the OS is outputted to the decode means, the memory means, the digital-analog conversion means and the mixing means.
According to the fourth mode of the present invention thus constructed, furthermore, the write enable signal is outputted on the basis of the first vertical synchronizing signal, the horizontal write clear signal, the horizontal write dot clock signal, the horizontal write starting signal, the horizontal write number signal, the vertical write starting signal, the vertical write number signal and the vertical write line clock signal. While the horizontal write starting signal and the vertical write starting signal are being outputted, the first luminance signal, which is digitized by the horizontal write dot clock signal, is written in the area of the video memory, which is specified by the address signal, the write shift signal and the write line increment signal.
According to the fifth mode of the present invention thus constructed, furthermore, when the operations of the fourth mode of the present invention are to be accomplished, the control means sets the value of the block, the frequency of the vertical write line clock signal, the preset value of the horizontal write starting counter, the preset value of the horizontal write number counter, the preset value of the vertical write starting counter, and the preset value of the vertical write number counter.
According to the sixth mode of the present invention thus constructed, furthermore, the still image means does not output the first vertical synchronizing signal to the video memory, the vertical write offset counter, the vertical write line clock generator, the vertical write starting counter and the vertical write number counter in accordance with the operations of the operation means.
According to the seventh mode of the present invention thus constructed, when the write control unit writes the second luminance signal in the video memory, the write control means controls the video memory. Then, the luminance signal selection means outputs the first luminance signal and the second luminance signal selectively to the video memory. The video memory control signal selection unit outputs the write control signals of the first luminance signal and the second luminance signal selectively in response to the selected output of the first and second luminance signals.
According to the eighth mode of the present invention thus constructed, furthermore, the read control unit and the FIFO read control unit control the reading of the luminance signal from the video memory into the FIFO memory in accordance with the control of the control means.
Accordingly to the ninth mode of the present invention thus constructed, furthermore, the read enable signal output circuit outputs the read enable signal on the basis of the third vertical synchronizing signal, the horizontal read reset signal, the vertical read line clock signal and the superimpose starting signal to read out the luminance signal from the area of the video memory, which is specified by either the horizontal reference read dot clock signal or the horizontal read dot clock signal and the read line increment signal. Then, the video switch is switched on the basis of the superimpose starting signal to selectively output the luminance signal, which is read out from the video memory and analogly converted by the digital-analog converter, and the third luminance signal.
According to the tenth mode of the present invention thus constructed, furthermore, the aforementioned horizontal reference read dot clock generator, the horizontal read dot clock generator and vertical read line clock generator are constructed of PLL circuits.
According to the eleventh mode of the present invention thus constructed, furthermore, the control means the individual clock numbers to be counted by the first horizontal read starting counter, the horizontal read number counter, the vertical blanking number counter, the vertical read starting counter and the vertical read number counter.
According to the twelfth mode of the present invention thus constructed, furthermore, the luminance signal, which is analogly converted by the digital-analog converter, and the third luminance signal are selectively outputted like the ninth mode of the present invention.
According to the fifteenth mode of the present invention thus constructed, furthermore, the first luminance signal digitized by the horizontal write dot clock signal is written line the fourth mode of the present invention in the area of the video memory, which is specified by the address signal, the write shift signal and the write line increment signal.
According to the eighteenth mode of the present invention thus constructed, furthermore, the luminance signal, which is read out from the video memory and analogly converted by the digital-analog converter, and the third luminance signal are selectively outputted like the ninth mode of the present invention.
According to the twenty first mode of the present invention thus constructed, furthermore, the luminance signal, which is analogly converted by the digital-analog converter, and the third luminance signal are selectively outputted like the twelfth mode of the present invention.
As has been described hereinbefore, according to the present invention, the decode means separates the first video signal into the first luminance signal, the first horizontal synchronizing signal and the first vertical synchronizing signal and subjects them to the analog-digital conversions. Moreover, the digital-analog conversion means analogly converts the luminance signal, which is stored in the memory means, and the mixing means reads out it from the memory means to output either the converted to analog luminance signal or the second luminance signal selectively as the third luminance signal. Thus, there can be attained an effect to provide an image processing system capable of displaying an image corresponding to the first luminance signal in a desired position, with a desired size and at a desired timing with respect to the image corresponding to the second luminance signal.
Since, moreover, the individual component means are constructed over the one extended slot card, it is possible to provide a compact image processing system.
Thus, on the basis of the first vertical synchronizing signal, the horizontal write clear signal, the horizontal write dot clock signal, the horizontal write starting signal, the horizontal write number signal, the vertical write starting signal, the vertical write number signal and the vertical write line clock signal, the write enable signal is outputted so that the first luminance signal can be written in a desired position and with a desired size, while the horizontal write starting signal and the vertical write starting signal are being outputted, in the area of the video memory, which is specified by the address signal, the write shift signal and the write line increment signal.
Furthermore, the first vertical synchronizing signal is not outputted to the video memory, the vertical write offset counter, the vertical write line clock generator, the vertical write starting counter and the vertical write number counter so that a still image can be easily obtained.
Furthermore, not only the first luminance signal but also the second luminance signal outputted from the control means can be written.
Furthermore, the control means can easily read the first luminance means in accordance with the control of the control means without obstructing the output of that first luminance signal to the monitor.
Furthermore, the video switch is switched on the basis of the superimpose starting signal to selectively output the first luminance signal, which is read out from the video memory and converted to analog by the digital-analog converter, and the third luminance signal.
Furthermore, it is possible to accomplish the so-called xe2x80x9cdouble superimposexe2x80x9d, in which the first luminance signal is superimposed upon the third luminance signal whereas the third luminance signal is further superimposed upon the first luminance signal. Thus, the switching is made on the basis of the signal so that the first luminance signal, which is read out from the video memory and converted to analog by the digital-analog converter, and the third luminance signal can be selectively outputted.